Known methods of driving a display device provided with a pixel section in which a plurality of pixels are arranged two-dimensionally in a matrix form at respective intersections between a plurality of scanning signal lines and a plurality of data signal lines include the SSD (Source Shared Driving) method. In this driving method, a plurality of data signal lines in a group are driven by a common data output circuit. For example, data signal lines for R, G and B are provided respectively, and the data signal lines for R, G and B which form a set of colors in each group are driven by a data output circuit in a data signal line driving circuit provided in each group in common among R, G and B. By this data output circuit, data is output to data signal lines for R, G and B in this order for each group. Here, in order to ensure the time for writing data signals from each data signal line to a pixel while increasing the driving speed, the data signal lines in the same color of respective groups are driven at the same time. According to the foregoing driving method, to meet a demand for higher resolution of a display device in which a large number of data signal lines are closely packed together, it is possible to reduce a size of the data signal line driving circuit without reducing the driving speed.
FIG. 9 illustrates an example structure of a display panel 1 of the liquid crystal display device adopting the SSD method. This display panel 1 is driven by a scanning signal line driving circuit (not shown) and a data signal line driving circuit 17, and includes a plurality of scanning signal lines GL and a plurality of data signal lines (source bus lines) RSL, GSL and BSL arranged in a matrix form. In FIG. 9, the scanning signal lines GL are designated as GL1, GL2 and GLn in this order from the side of the data signal line driving circuit 17 (from the top of the sheet of FIG. 9). A plurality of data signal lines are divided into groups of data signal lines RSL, GSL and BSL, some of the groups of the data signal lines are shown in FIG. 9 and indicated from the left end, as data signal lines RSLn−1, GSLn−1 and BSLn−1 in the n−1th group, data signal lines RSLn, GSLn and BSLn in the nth group, and data signal lines RSLn+1, GSLn+1 and BSLn+1 in the n+1th group.
Pixels PIX are provided at respective intersections between the scanning signal lines GL and the data signal lines RSL, GSL and BSL two-dimensionally to form a pixel section 11. Each pixel PIX includes a TFT 12, a liquid crystal capacitance 13 and an auxiliary capacitance 14, and the liquid crystal capacitance 13 and the auxiliary capacitance 14 are connected to the data signal line RSL, GSL or BSL via the TFT 12. The gate of each TFT 12 is connected to the scanning signal line GL. Incidentally, the electrode on the side of the TFT 12 of the liquid crystal capacitance 13 serves as a common electrode. Furthermore, the electrode of the auxiliary capacitance 14 facing the electrode of the TFT 12 is connected to an auxiliary capacitance line CsL.
The respective ends of the data signal lines RSL, GSL, BSL on the side of the data signal line driving circuit 17 (on the upstream side in the direction of supplying data signal) are connected to analog switches ASW. As shown in FIG. 9, analog switches ASWRn−1 , ASWGn−1 and ASWBn−1 are provided corresponding to RSLn−1, GSLn−1 and BSLn−1, analog switches ASWRn, ASWGn and ASWBn are provided corresponding to data signal lines RSLn, GSLn and BSLn, and analog switches ASWBn+1 are provided corresponding to data signal lines RSLn+1, GSLn+1 and BSLn+1.
The analog switch ASWR connected to the data signal line RSL for R is switched ON/OFF by a switching signal Ron, the analog switch ASWG connected to the data signal line GSL for G is switched ON/OFF by a switching signal Gon, and the analog switch ASWB connected to the data signal line BSL for B is switched ON/OFF by a switching signal Bon. A control circuit 18 is provided for outputting these switching signals Ron, Gon and Bon.
Here, respective terminals of the analog switches ASWR, ASWG and ASWB in the same group of data signal lines on the opposite side of the data signal lines (on the upstream side in the direction of supplying a data signal) are mutually connected by a common wiring 15. In FIG. 9, the corresponding group numbers are given as subscripts to the common wirings 15. These common wirings 15 are connected to respective data output circuits DOAn−1, DOAn and DOAn+1 provided for each group in the data signal line driving circuit 17. Namely, each of these data output circuits DOAn−1, DOAn and DOAn+1 is used in common among all the data signal lines in the same group. In FIG. 9, the analog switches ASWRn−1, ASWGn−1 and WSBn−1 are connected to the data output circuit DoAn−1 which outputs data DATAn−1, the analog switches ASWRn, ASWGn and ASWBn are connected to the data output circuit DoAn which outputs data DATAn, and the analog switches ASWRn+1, ASWGn+1 and ASWBn+1 are connected to the data output circuit DOAn+1 which outputs data DATAn+1.
The respective analog switches ASW in the same group are switched ON/OFF so that the ON period transits in the order of R, G and B, for example, and the ON/OFF of the supply of the data from the common data output circuit DOA to the data signal lines changes among R, G and B. As described, a data switching section 16 made up of three data switches is provided for each group of data signal lines. In FIG. 9, the corresponding group number is given as a subscript to the data switching section 16.
Next, the method of driving the liquid crystal display device will be explained. Specifically, the supply of a data signal in a certain horizontal period, i.e., to a data signal line for one scanning period will be explained. FIG. 10 shows a timing chart. In the data switching sections 16 shown in FIG. 10, switching signals Ron, Gon and Bon are supplied by time-division, and in synchronous with the supply of these signals, the data DATAn is input as the DATAn(R), DATAn(D) and DATAn(B). In the certain horizontal period 1H, a scanning signal line GLi is selected, and the ON period of the switching signal transits in each group of data signal lines in the order of Ron→Gon→Bon, thereby outputting data to the data signal lines in the order of DATAn(R)→DATAn(D)→DATAn(B).
Here, adopted is the method of driving liquid crystal, called “1H inversion driving”, wherein the data DATA is selected in each horizontal period, for example, from the positive-polarity potential range of 6 V to 10.5 V and the negative-polarity potential range of 1.5 V to 6 V. Generally, a liquid crystal material for use in the liquid crystal display device alternates a voltage to be applied to a liquid crystal material. In the conventional driving method, one of the potentials to be supplied to the liquid crystal material is set the potential of the data DATA, and the other potential is set around 6 V. In the certain horizontal period (1H), the data DATA having the positive-polarity potential (6 V to 10.5 V) is supplied, and in the subsequent horizontal period (1H), the DATA having the negative-polarity potential (1.5 V to 6 V) is supplied. In the next frame, the data DATA whose polarity is inversed is supplied, and the AC driving of the liquid crystal is performed. In FIG. 10, in a certain frame, the negative-polarity data DATA is supplied to the data signal line in the previous horizontal period, and in the subject horizontal period, the positive-polarity DATA is supplied.
FIG. 11 illustrates an example structure of a display panel 2 of another liquid crystal display device in which driving is performed by the SSD method. The members having the same reference numerals as those of the liquid crystal panel 1 shown in FIG. 9 are designated as the same reference numerals. In FIG. 11, the adjoining odd-numbered data signal line OSL and the even-numbered data signal line ESL form a pair. The terminal of the data signal line OSL on the side of the data signal line driving circuit 27 (upstream side in the direction of supplying data signal) is connected to the analog switch ASWO, and the terminal of the data signal line ESL on the side of the data signal line driving circuit 27 (on the upstream side in the direction of supplying data) is connected to the analog switch ASWE. The analog switch ASWO is switched ON/OFF by the switching signal ODDon, and the analog switch ASWE is switched ON/OFF by the switching signal EVENon.
Here, respective terminals of the analog switches ASWO and ASWE in the same group of data signal lines on the opposite side of the data signal lines (on the upstream side in the direction of supplying data signal) are connected via the common wiring 25. This common wiring 25 is connected to the data output circuit DOB provided in the data signal line driving circuit 27 for each group. Namely, each data output circuit DOB is used in common among all the data signal lines in the same group. This data output circuit DOB outputs the data DATA. The analog switches ASW in the same group are switched ON/OFF so that the ON period transits in the order of ASWO to ASWE, for example, and whether the data is supplied or not supplied from the common data output circuit to the data signal line is switched between the odd-numbered data signal line and the even-numbered data signal line. As described, a data switching section 26 made up of two data switches is provided for each group of data signal lines.
FIG. 12 shows a timing chart of driving the liquid device adopting the 1H inversion driving. In the data switching sections 26 shown in FIG. 12, switching signals ODDon, EVENon are supplied by time-division from the control circuit 28. In synchronous with the supply of these switching signals ODDon and EVENon, the data DATAn in the nth group is input as DATAn (ODD) and DATAn(EVEN). In the certain horizontal period 1H, the gate signal line GLi is selected, and in this period, the ON period of the switching signal in each group of the data signal lines transits in the order of ODDon to EVENon, and the data is output to the data signal line in the order of DATAn(ODD) to DATAn(EVEN).
The following documents are listed for the relevant prior art documents.    (Document 1)
Japanese Unexamined Patent Publication No. 11-338438/1999 (Tokukaihei 11-338438), published on Dec. 10, 1999.    (Document 2)
Japanese Unexamined Patent Publication No. 10-39278/1998 (Tokukaihei 10-39278), published on Feb. 13, 1998.    (Document 3)
U.S. Patent Application Publication No. US 2001/0020929 A1).
The timing chart of FIG. 10 will be explained in more details. When the switching signals Ron, Gon and Bon are sent by time-division, and the data DATAn(R), DATAn(D) and DATAn(B) are supplied to the data signal lines RSLn, GSLn and BSLn, first, the data DATAn(R) is supplied to the data signal line RSLn by the switching signal Ron, and the data signal line RSLn is stably charged to the potential of the data DATAn(R). By the switching signals Gon and Bon, the analog switches ASWGn and ASWBn are set in the OFF state, and the data signal lines GSLn and BSLn are set in the floating state, and the data signal lines RSLn, GSLn and BSLn are subjected to capacitive coupling. Therefore, for example, with a sudden increase in potential of the data signal line RSLn, the respective potentials of the adjacent data signal line BSLn−1 and GSLn in the floating state, and the potential of the data signal line BSLn are subjected to fluctuations. In FIG. 10, the foregoing potential fluctuations are not shown.
Next, the switching signal Ron is not supplied, and the switching signal Gon is supplied to supply the data DATAn(G) to the data signal line GSLn. This data signal line GSLn is stably charged to the potential of the data DATAn(G); however, the analog switch ASWRn is switched in the OFF state by the switching signal Ron, and the data signal line RSLn is set in the floating state. Therefore, the potential of the data signal line RSLn changes by ΔV1, and this change in potential is referred to as up-throw potential fluctuations ΔV1. The respective potentials of the adjacent data signal line BSLn−1 and BSLn are also subjected to fluctuations at the same time. The foregoing potential fluctuations are not shown in FIG. 10.
Next, the switching signal Gon is not supplied, and the switching signal Bon is supplied to supply the data DATAn(B) to the data signal line BSLn. The data signal line BSLn is stably charged to the potential of the data DATAn(B). By the switching signals Ron and Gon, the analog switches ASWRn and ASWRn are set in the OFF state, and the data signal lines RSLn and GSLn are set in the floating state, and the data signal lines RSLn, GSLn and BSLn are subjected to capacitive coupling. Therefore, the data signal line RSLn is subjected to further up-throw potential fluctuations from the state where the data DATAn(R) is supplied to the data signal line RSLn from ΔV1 to ΔV2, due to the potentials of the data signal line BSLn−1 and the potential of the data signal line GSLn. Similarly, the potential of the data signal line GSLn is subjected to the up-throw potential fluctuations by ΔV3 due to the potentials of the data signal line RSLn−1 and the potential of the data signal line BSLn from the state where the data DATAn(G) is supplied to the data signal line GSLn.
As described, when data are sequentially supplied to the data signal lines by time division, only the most currently charged data DATAn(B) is charged without being affected by up-throw potential fluctuations due to capacitive coupling, and upon completing the function of the scanning signal for controlling the charge of the pixel in one horizontal period, the color in the potential of the pixel as charged is displayed in the display section. Here, as explained above, the up-throw potential fluctuations ΔV due to the capacitive coupling are accumulated corresponding to respective data signal lines by the order of the supply period of the switching signal Ron→Gon→Bon. Therefore, for example, when an attempt is made to display in an intermediate tone (gray), by setting the data DATAn(R), DATAn(G) and DATAn(B) to the same potential, the respective potentials of VRSLn, VGSLn and VBSLn of the final data signal lines RSLn, GSLn and BSLn hold the relationship of VRSLn>VGSLn>VBSLn. Here, in the case where the liquid crystal display is in a normally while mode, it is displayed in dark bluish gray. In response to the foregoing problem, the prior art document 1 adopts the means of altering the order of switching the switches in recognizing the importance in the wavelength dependency of a liquid crystal material.
In the driving method shown in the timing chart of FIG. 12, when the data signal is supplied to the data signal line ESLn, the data signal line OSLn after having the data DATAn (ODD) supplied are subjected to up-throw potential fluctuations by ΔV11.
As described, the conventional driving methods wherein the potential of the data signal line is changed significantly in the positive direction and the negative direction at each horizontal period by the 1H inversion driving present the problem in that up-throw potential fluctuations ΔV become large, resulting in poor display quality due to changes in color.
Furthermore, when supplying negative-polarity data to the data signal lines RSLn, GSLn and BSLn, down-throw potential fluctuations occur in a direction opposite to the positive-polarity.
The foregoing up-throw potential fluctuations ΔV are noticeable in a display device wherein a large number of data signal lines are closely packed together, and electrostatic capacitive coupling between the data signal lines is strong, such as a liquid crystal display device adopting the SSD method.